Visible to Intel only — GUID: bhc1395127793769
Ixiasoft
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
Visible to Intel only — GUID: bhc1395127793769
Ixiasoft
5.2. Speed Selection Signal
Signal | Operating Mode | Direction | Width | Description |
---|---|---|---|---|
speed_sel | 1G/2.5G, 10M/100M/1G/2.5G/5G/10G (USXGMII), 10M/100M/1G/2.5G | In | 3 | Connect this asynchronous signal to the PHY to obtain the PHY's speed:
The speed_sel signal can be synchronized to TX or RX clock of the LL Ethernet 10G MAC Intel® FPGA IP core. Before the speed change, make sure the MAC TX and RX datapaths are idle with no packet transmission. After the line rate changes, trigger a reset on the TX and RX datapaths by asserting these active-low reset signals, tx_rst_n and rx_rst_n. |