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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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3.6.2. Priority-Based Flow Control
Follow these steps to use the priority-based flow control (PFC):
- Turn on the Priority-based flow control (PFC) parameter and specify the number of priority levels using the Number of PFC priorities parameter. You can specify between 2 to 8 PFC priority levels.
- Set the following registers.
- On the TX datapath:
- Set tx_pauseframe_enable to 0 to disable the IEEE 802.3 flow control.
- Set tx_pfc_priority_enable[n] to 1 to enable the PFC for priority queue n.
- On the RX datapath:
- Set the IGNORE_PAUSE bit in the rx_frame_control register to 1 to disable the IEEE 802.3 flow control.
- Set the rx_pfc_control[7:0] register bits to 0 to enable the PFC. Most of the rest of the bits are unused.
- On the TX datapath:
- Connect the avalon_st_tx_pfc_gen_data signal to the corresponding RX client logic and the avalon_st_rx_pfc_pause_data signal to the corresponding TX client logic.
- You have the option to configure the MAC RX to forward the PFC frame to the client by setting the rx_pfc_control[16] register to 1. By default, the MAC RX drops the PFC frame after processing it.
You must handle the XON/XOFF requests in the following manner:
- Assert the XOFF, which runs at the clock frequency of 312.5 MHz, for at least 1 clock cycle, which runs at the clock frequency of 312.5 MHz to ensure that the PFC frame can transfer successfully.
- Assert the XON, which runs at the clock frequency of 312.5 MHz, for at least 25 clock cycle to ensure that the PFC frame can transfer successfully.