Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

Download PDF
ID 813663
Date 4/01/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview 2. Getting Started 3. Functional Description 4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 5. Interface Signals 6. Configuration Registers 7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview x
1.1. Features 1.2. Release Information 1.3. Low Latency Ethernet 10G MAC Operating Modes 1.4. Device Family Support 1.5. Performance and Resource Utilization
1.5. Performance and Resource Utilization x
1.5.1. Resource Utilization 1.5.2. TX and RX Latency
2. Getting Started x
2.1. Introduction to Intel® FPGA IP Cores 2.2. Installing and Licensing Intel® FPGA IP Cores 2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Generated File Structure 2.5. Simulating Intel® FPGA IP Cores 2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core 2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core x
2.6.1. Design Considerations
2.6.1. Design Considerations x
2.6.1.1. Timing Constraints
2.6.1.1. Timing Constraints x
2.6.1.1.1. Pseudo-Static CSR Fields 2.6.1.1.2. Clock Crosser 2.6.1.1.3. Dual Clock FIFO
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples x
2.7.1. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Example for Agilex™ 5 Devices
3. Functional Description x
3.1. Architecture 3.2. Interfaces 3.3. Frame Types 3.4. TX Datapath 3.5. RX Datapath 3.6. Flow Control 3.7. Reset Requirements 3.8. XGMII Error Handling (Link Fault) 3.9. IEEE 1588v2
3.4. TX Datapath x
3.4.1. Padding Bytes Insertion 3.4.2. Address Insertion 3.4.3. CRC-32 Insertion 3.4.4. XGMII Encapsulation 3.4.5. Inter-Packet Gap Generation and Insertion 3.4.6. XGMII Transmission 3.4.7. TX Promiscuous (Transparent) Mode 3.4.8. TX Timing Diagrams
3.5. RX Datapath x
3.5.1. XGMII Decapsulation 3.5.2. CRC Checking 3.5.3. Address Checking 3.5.4. Frame Type Checking 3.5.5. Length Checking 3.5.6. CRC and Padding Bytes Removal 3.5.7. Overflow Handling 3.5.8. RX Promiscuous (Transparent) Mode 3.5.9. RX Timing Diagrams
3.5.5. Length Checking x
3.5.5.1. Frame Length 3.5.5.2. Payload Length
3.6. Flow Control x
3.6.1. IEEE 802.3 Flow Control 3.6.2. Priority-Based Flow Control
3.6.1. IEEE 802.3 Flow Control x
3.6.1.1. Pause Frame Reception 3.6.1.2. Pause Frame Transmission
3.6.2. Priority-Based Flow Control x
3.6.2.1. PFC Frame Reception 3.6.2.2. PFC Frame Transmission
3.9. IEEE 1588v2 x
3.9.1. Architecture 3.9.2. TX Datapath 3.9.3. RX Datapath 3.9.4. Frame Format
3.9.4. Frame Format x
3.9.4.1. PTP Packet in IEEE 802.3 3.9.4.2. PTP Packet over UDP/IPv4 3.9.4.3. PTP Packet over UDP/IPv6
5. Interface Signals x
5.1. Clock and Reset Signals 5.2. Speed Selection Signal 5.3. Error Correction Signals 5.4. Avalon® Memory-Mapped Interface Programming Signals 5.5. Avalon® Streaming Data Interfaces 5.6. Avalon® Streaming Flow Control Signals 5.7. Avalon® Streaming Status Interface 5.8. PHY-side Interfaces 5.9. IEEE 1588v2 Interfaces
5.5. Avalon® Streaming Data Interfaces x
5.5.1. Avalon® Streaming TX Data Interface Signals 5.5.2. Avalon® Streaming RX Data Interface Signals 5.5.3. Avalon® Streaming Data Interface Clocks
5.7. Avalon® Streaming Status Interface x
5.7.1. Avalon® Streaming Interface TX Status Signals 5.7.2. Avalon® Streaming Interface RX Status Signals
5.8. PHY-side Interfaces x
5.8.1. XGMII TX Signals 5.8.2. XGMII RX Signals 5.8.3. GMII TX Signals 5.8.4. GMII RX Signals 5.8.5. Clock Enable Signals
5.9. IEEE 1588v2 Interfaces x
5.9.1. IEEE 1588v2 Egress TX Signals 5.9.2. IEEE 1588v2 Ingress RX Signals 5.9.3. IEEE 1588v2 Interface Clocks
6. Configuration Registers x
6.1. Register Map 6.2. Register Access Definition 6.3. Primary MAC Address 6.4. MAC Reset Control Register 6.5. TX Configuration and Status Registers 6.6. Flow Control Registers 6.7. RX Configuration and Status Registers 6.8. ECC Registers 6.9. Statistics Registers 6.10. Timestamp Registers
6.10. Timestamp Registers x
6.10.1. Calculating PHY Total Latency 6.10.2. Calculating Deterministic Latency 6.10.3. PTP Register Configuration
1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs

6.10. Timestamp Registers

The TX and RX timestamp registers are available when you turn on the Enable time stamping parameter. Otherwise, these registers are reserved.
Table 41.  Timestamp Registers
Word Offset Register Name Description Access HW Reset Value
0x0100 tx_period_10g Specifies the clock period for the timestamp adjustment on the transmit datapaths when operating at 10G PHY speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds (tx_period_fns).
  • Bits 16 to 19—period in nanoseconds (tx_period_ns).
  • Bits 20 to 31—reserved.
The default value is 3.2 ns for 312.5 MHz clock. 		RW 0x33333
0x0102 tx_adj_fns_10g Static timing adjustment in fractional nanoseconds on the transmit datapaths when operating at 10G PHY speed.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 31 to 16—reserved.
 RW 0x0
0x0104 tx_adj_ns_10g Static timing adjustment in nano seconds on the transmit datapaths when operating at 10G PHY speed.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved.
 RW 0x0
0x0108 tx_period_1g_100m_10m Specifies the clock period for the timestamp adjustment on the transmit datapaths when operating at 1G/2.5G/10M/100M speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and GMII bus.
  • Bits 0 to 15—period in fractional nanoseconds (tx_period_fns).
  • Bits 16 to 19—period in nanoseconds (tx_period_ns).
  • Bits 20 to 31—reserved.
The default value is 8 ns for 125 MHz clock. This is reserved on 1G/2.5G and 1G/2.5G/10G variants. 		RW 0x80000
0x010A tx_adj_fns_1g_100m_10m Static timing adjustment in fractional nanoseconds on the transmit datapaths when operating at 1G/2.5G/10M/100M speed.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—unused.
 RW 0x0
0x010C tx_adj_ns_1g_100m_10m Static timing adjustment in nanoseconds on the transmit datapaths when operating at 1G/2.5G/10M/100M speed.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved.
 RW 0x0
0x110 tx_asymmetry Specifies the asymmetry value and direction of arithmetic operation.
  • Bits 0 to 16—asymmetry value.
  • Bit 17—direction.
    • Set to 0—add asymmetry value to correction field (CF).
    • Set to 1—minus asymmetry value from CF.
  • Bit 18—enable bit.
  • Bit 19 to 31—reserved.
 RW 0x0
0x112 tx_p2p

Specifies the direction of arithmetic operation for meanPathDelay.

  • Bit 0— direction.
    • Set to 0—add meanPathDelay value to CF.
    • Set to 1—minus meanPathDelay value from CF.
  • Bit 1 to 31—reserved.
 RW 0x0
0x114 tx_cf_err_stat
  • Bits 0—error status bit to indicate that ingress correction field is equal to the absolute maximum, 64'h7FFF_FFFF_FFFF_FFFF.
  • Bit 16—error status bit to indicate that egress correction field is equal or larger than absolute maximum, 64’h7FFF_FFFF_FFFF_FFFF.
  • Bit 17—error status bit to indicate that residence time is equal or larger than 4 seconds.
  • Bit 18—error status bit to indicate that residence time is a negative value.
 RW1C 0x0
0x0120 rx_period_10g Specifies the clock period for the timestamp adjustment on the receive datapaths when operating at 10G speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and XGMII bus.
  • Bits 0 to 15—period in fractional nanoseconds (rx_period_fns).
  • Bits 16 to 19—period in nanoseconds rx_period_ns.
  • Bits 20 to 31—reserved.
The default value is 3.2 ns for 312.5 MHz clock. 		RW 0x33333
0x0122 rx_adj_fns_10g Static timing adjustment in fractional nanoseconds on the receive datapaths when operating at 10G speed.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—unused.
 RW 0x0
0x0124 rx_adj_ns_10g Static timing adjustment in nanoseconds on the receive datapaths when operating at 10G speed.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved.
 RW 0x0
0x0128 rx_period_1g_100m_10m Specifies the clock period for the timestamp adjustment on the receive datapaths when operating at 1G/2.5G/10M/100M speed. The MAC IP core multiplies the value of this register by the number of stages separating the actual timestamp and GMII bus.
  • Bits 0 to 15—period in fractional nanoseconds (rx_period_fns).
  • Bits 16 to 19—period in nanoseconds rx_period_ns.
  • Bits 20 to 31—reserved.
The default value is 8 ns for 125 MHz clock. This is reserved in 1G/2.5G and 1G/2.5G/10G variants. 		RW 0x80000
0x012A rx_adj_fns_1g_100m_10m Static timing adjustment in fractional nanoseconds on the receive datapaths when operating at 1G/2.5G/10M/100M speed.
  • Bits 0 to 15—adjustment period in fractional nanoseconds.
  • Bits 16 to 31—reserved.
 RW 0x0
0x012C rx_adj_ns_1g_100m_10m Static timing adjustment in nanoseconds on the receive datapaths when operating at 1G/2.5G/10M/100M speed.
  • Bits 0 to 15—adjustment period in nanoseconds.
  • Bits 16 to 31—reserved.
 RW 0x0
0x12E rx_p2p_mpd_ns

meanPathDelay valid and value in ns.

The peer-to-peer mechanism delivers meanPathDelay for each ingress port. This needs to be added to the Sync packet’s correction field before the packet is sent out on egress port. Thus, the egress port might add any of the ingress ports' 'meanPathDelay'. The value to be added at the egress port should correspond to the ingress port on which the Sync packet has arrived.

  • Bit 30—Indicates meanPathDelay is valid.
  • Bits 0 to 29—meanPathDelay value in nanosecond.
RW 0x0
0x130 rx_p2p_mpd_fns

meanPathDelay value in fns.

  • Bits 0 to 15—meanPathDelay value in fractional nanosecond.
RW 0x0

Section Content
Calculating PHY Total Latency
Calculating Deterministic Latency
PTP Register Configuration

Level Two Title