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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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1.1. Features
This Intel® FPGA IP core is designed to the IEEE 802.3–2008 Ethernet Standard available on the IEEE website (www.ieee.org). All LL 10GbE Intel® FPGA IP core variations include MAC only and are in full-duplex mode. These Intel® FPGA IP core variations offer the following features:
- MAC features:
- Full-duplex MAC in three operating modes: 1G/2.5G, 10M/100M/1G/2.5G/5G/10G (USXGMII), and 10M/100M/1G/2.5G.
- Variation for selected operating modes: MAC TX and MAC RX block.
- Programmable promiscuous (transparent) mode.
- Priority-based flow control (PFC) with programmable pause quanta. PFC supports 2 to 8 priority queues.
- Interfaces:
- Client-side—32-bit Avalon® streaming interface.
- Management—32-bit Avalon® memory-mapped interface.
- PHY-side—32-bit XGMII for 10 GbE and 16-bit GMII for 2.5 GbE and 1GbE.
- Frame structure control features:
- Virtual local area network (VLAN) and stacked VLAN tagged frames decoding (type 'h8100).
- Cyclic redundancy code (CRC)-32 computation and insertion on the TX datapath. Optional CRC checking and forwarding on the RX datapath.
- Deficit idle counter (DIC) for optimized performance with average inter-packet gap (IPG) for LAN applications.
- Supports programmable IPG.
- Ethernet flow control using pause frames.
- Programmable maximum length of TX and RX data frames up to 64 Kbytes (KB).
- Preamble passthrough mode on TX and RX datapaths, which allows user defined preamble in the client frame.
- Optional padding insertion on the TX datapath and termination on the RX datapath.
- Frame monitoring and statistics:
- Optional CRC checking and forwarding on the RX datapath.
- Optional statistics collection on TX and RX datapaths.
- Optional timestamping as specified by the IEEE 1588v2 standard for the following configurations:
- 1G/2.5GbE MAC with 1G/2.5G Multirate Ethernet PHY IP core
- 10M/100M/1G/2.5G/5G/10G (USXGMII) MAC