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1. Low Latency Ethernet 10G MAC Intel® FPGA IP Overview
2. Getting Started
3. Functional Description
4. Parameter Settings for the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
5. Interface Signals
6. Configuration Registers
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® FPGA IP User Guide: Agilex™ 5 FPGAs and SoCs
2.1. Introduction to Intel® FPGA IP Cores
2.2. Installing and Licensing Intel® FPGA IP Cores
2.3. Specifying the IP Core Parameters and Options ( Quartus® Prime Pro Edition)
2.4. Generated File Structure
2.5. Simulating Intel® FPGA IP Cores
2.6. Upgrading the Low Latency Ethernet 10G MAC Intel® FPGA IP Core
2.7. Low Latency Ethernet 10G MAC Intel® FPGA IP Design Examples
5.1. Clock and Reset Signals
5.2. Speed Selection Signal
5.3. Error Correction Signals
5.4. Avalon® Memory-Mapped Interface Programming Signals
5.5. Avalon® Streaming Data Interfaces
5.6. Avalon® Streaming Flow Control Signals
5.7. Avalon® Streaming Status Interface
5.8. PHY-side Interfaces
5.9. IEEE 1588v2 Interfaces
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3.7. Reset Requirements
The MAC IP core consists of the following reset domains:
- CSR reset—global reset,
- MAC TX reset, and
- MAC RX reset.
These resets are asynchronous events. When the MAC or any part of it goes into reset, the user application must manage possible asynchronous changes to the states of the MAC interface signals. The MAC does not guarantee any reset sequence. Intel recommends the sequence shown in the following diagram and table for CSR reset, and TX and RX datapaths reset respectively.
Figure 24. CSR Reset
No | Stage | Steps |
---|---|---|
1 | Ensure no data transfer in progress. |
|
2 | Trigger reset. |
|
3 | Stop reset. |
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4 | Resume data transfer. |
|
Note: During reset, the value of the avalon_st_tx_ready signal can be 0 or 1.