Visible to Intel only — GUID: wjb1663225605015
Ixiasoft
Visible to Intel only — GUID: wjb1663225605015
Ixiasoft
7.2. Port Registers
Base Address | Word/Byte Offset | Description |
---|---|---|
0x000_0000 EHIPLANE/EHIPCORE – Ethernet Reconfiguration (Word offset) |
0x0B0-0x0E8 | Auto Negotiation and Link Training registers |
0x300-0x3FF | PHY registers | |
0x310-0x310 | Reset Controller Register | |
0x400-0x4FF | TX MAC registers | |
0x500-0x5FF | RX MAC registers | |
0x600-0x7FF | Pause and Priority- Based Flow Control registers | |
0x800-0x8FF | TX Statistics Counter registers | |
0x900-0x9FF | RX Statistics Counter registers | |
0xA00-0xAFF | TX 1588 PTP registers | |
0xB00-0xBFF | RX 1588 PTP registers | |
0x000_4000 RS-FEC– RSFEC Reconfiguration (Byte offset) |
0x000-0x2FF | TX and RX RS-FEC registers |
0x004_0000 PHY– XCVR Reconfiguration (Byte offset) |
0x000-0x144 |
For non-PTP channels: PMA Capability registers (0x40000-0x40144) For PTP channels: PTP reconfiguration registers |
0x005_0000 PHY– XCVR Reconfiguration (Byte offset) |
0x000-0x207 | PMA Avalon® Mapped-memory registers |
0x006_1000 (Byte offset) |
0x100-0x1FF | PTP Packet Classifier |
0x006_2000 | - | Reserved |
For more information on Ethernet registers, refer to section 2.12 of E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs.
For more information on RS-FEC registers, refer to section 9.5 of E-Tile Transceiver PHY User Guide.
For more information on PMA registers, refer to section 9.1 of E-Tile Transceiver PHY User Guide.
Ethernet reconfiguration registers use 32-bit addresses while RS-FEC and PMA registers are byte addressable. All registers can be internally routed to respective reconfiguration interface depending on the address range. The Port Registers address mapping for each port shares the same offset as shown in table Port Register Base Addresses above with different port base address, listed in table Table 44. For example, base address of Port 0 starts at 0x020_0000, and base address of Port 4 is 0x120_0000.
The effective address of a register is port base address + port register offset. If the register address is in word offset, the address must be multiplied with four, plus the port base address. If the register address is in byte offset (for example PTP registers), the offset can be added to port base address without multiplication. To access these registers, you can write bit 2-25 of the effective address to HSSI Control/Address Register with set_csr or get_csr SAL command.
Interface | Data Bus width | Register Size | Write Access | Read Access |
---|---|---|---|---|
Ethernet Reconfiguration (Word offset) | 32-bit | 4 bytes | Wstrb is not supported. AXI- Lite write will write full 32b. Register offset must be multiplied with four. |
AXI-Literead will read full 32b. Register offset must be multiplied with four. |
RS-FEC Reconfiguration (Byte offset) | 8-bit | 4 bytes | Wstrb is supported. Single AXI transaction will split into maximum of 4 single byte write depending on wstrb. No multiplication required for address calculation. |
Single AXI transaction will split into 4 single byte read, e.g. AXI read address 0 will generate read byte 0, 1, 2 and 3. No multiplication required for address calculation. |
XCVR Reconfiguration (Byte offset) |
8-bit | 1 byte | Wstrb is supported. Single AXI transaction will split into maximum of 4 single byte write depending on wstrb. No multiplication required for address calculation. |
Single AXI transaction will split into 4 single byte read, e.g. AXI read address 0 will generate read byte 0, 1, 2 and 3. No multiplication required for address calculation. |
PTP XCVR Reconfiguration(Bytes offset) |
16-bit | 1 byte | Wstrb is supported. Single AXI transaction will split into maximum of 4 single byte write depending on wstrb. Writedata: [7:0]- PTP Channel 4 [15:8]- PTP Channel 5 No multiplication required for address calculation. |
Single AXI transaction will split into 4 single byte read, e.g. AXI read address 0 will generate read byte 0, 1, 2 and3. Readdata: [7:0]- PTP Channel 4 [15:8]- PTP Channel 5 No multiplication required for address calculation. |
Example on Register Address Calculation:
- To access TX MAC Link Fault Configuration register of Port 4: TX MAC Link Fault Configuration register word offset = 0x405
Base address of Port 4 Ethernet Reconfiguration Register = 0x120_0000 AXI-Lite CSR read request address
=0x405*4 + 0x120_0000 = 0x120_1014 (byte addressing)
Write bit [25:2] of the calculated address to HSSI Control/Address Register Address field
=0x120_1014 / 4 = 0x48_0405
PTP Packet Classifier registers use the same access mechanism as Ethernet Reconfiguration registers.
- To access RS-FEC rsfec_top_tx_cfg register of Port 6:
rsfec_top_tx_cfg register byte offset = 0x10
Base address of Port 6 RS-FEC Reconfiguration Register = 0x160_4000
AXI-Lite CSR write request address
= 0x160_4000 + 0x10 = 0x160_4010 (single AXI-Lite write can generate maximum 4 single byte write access depending on write strobe)
AXI-Lite CSR read request address
= 0x160_4000 + 0x10 = 0x160_4010 (single AXI-Lite read will generate4 single byte read access to RS-FEC reconfiguration interface, e.g. read 1B from 0x160_4010, read 1B from 0x160_4011, read 1B from 0x160_4012, read 1B from 0x160_4013 and return all 32b through AXI-Lite in single request)
Write bit [25:2] of the calculated address to HSSI Control/Address Register Address field
=0x160_4010 / 4 = 0x58_1004
PMA Avalon® Mapped-memory and capability registers use the same access mechanism as RS-FEC registers. These registers will be internally routed to XCVR Reconfiguration interface or PTP XCVR Reconfiguration interface depending on the channel number.