Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 8/29/2023
Public

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8. Ethernet SS IP Example Design

The following figure shows the Example Design Tab of the Ethernet Subsystem IP GUI.
Figure 15. Ethernet SS IP Example Design Tab
Table 55.  E-Tile Supported Example Design VariantsThe following table shows the supported Example Design variants for the Ethernet SS IP in E-tile.
Data Rate Variant Simulation Compilation-Only Project Hardware Example Design
10GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
PCS Yes Yes Yes
OTN Yes Yes No
FlexE Yes Yes No
25GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
PCS Yes Yes Yes
OTN Yes Yes No
FlexE Yes Yes No
100GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
PCS Yes Yes Yes
OTN Yes Yes No
FlexE Yes Yes No
CPRI PCS Yes Yes Yes
PMA Yes Yes Yes
Table 56.  F-Tile Supported Example Design VariantsThe following table shows the supported Example Design variants for the Ethernet SS IP in F-tile.
Data Rate Variant Simulation Compilation-Only Project Hardware Example Design
10GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
10GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
25GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
40GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
50GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
100GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
200GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes
400GbE MAC+PCS Yes Yes Yes
PTP Yes Yes Yes