Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 8/29/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for Ethernet Subsystem Intel FPGA IP User Guide
Give Feedback

4.3.1.3. get_hssi_profile for F-Tile

This SAL command is used to poll the DR CSR Ready for New Trigger. The DR ready for trigger status is reflected in HSSI Command/Status CSR bit 3 following the write/read CSR sequence to HSSI Command/Status CSR as shown in the following table. This get_hssi_profile SAL command is executed in HW and not through SAL NIOS firmware to avoid extra latency introduced in the DR sequence.
Table 17.   get_hssi_profile
SAL command Write CSR Read CSR (polling) CSR Values
get_hssi_profile

HSSI Command/Status [0:0] = 1 (read command)

HSSI Command/Status [1:1] = 0 (write command)

HSSI Command/Status [2:2] = 0 (reset ACK_TRANS)

HSSI Command/Status [3:3] = 0 (not busy)

HSSI Command/Status [0:0] = 1 (read command)

HSSI Command/Status [1:1] = 0 (write command)

HSSI Command/Status [2:2] = 1 (transfer completed)

HSSI Command/Status [3:3] = 0 (not ready) or 1 (ready)

 dyn_rcfg_dr_trigger_reg [1:1] - Ready for trigger 0 = not ready 1 = ready
get_hssi_profile HSSI Write Data[31:24] = 1 HSSI Read Data[31:0] dyn_rcfg_dr_tx_fully_reset_ack_reg Values
get_hssi_profile HSSI Write Data[31:24] = 2 HSSI Read Data[31:0] dyn_rcfg_dr_tx_fully_reset_out_reset_reg Values
get_hssi_profile HSSI Write Data[31:24] = 3 HSSI Read Data[31:0] dyn_rcfg_dr_tx_reset_initial_reg Values
get_hssi_profile HSSI Write Data[31:24] = 4 HSSI Read Data[31:0] dyn_rcfg_dr_tx_src_alarm_reg Values
get_hssi_profile HSSI Write Data[31:24] = 5 HSSI Read Data[31:0] dyn_rcfg_dr_rx_fully_reset_ack_reg Values
get_hssi_profile HSSI Write Data[31:24] = 6 HSSI Read Data[31:0] dyn_rcfg_dr_rx_fully_reset_out_reset_reg Values
get_hssi_profile HSSI Write Data[31:24] = 7 HSSI Read Data[31:0] dyn_rcfg_dr_rx_reset_initial_reg Values
get_hssi_profile HSSI Write Data[31:24] = 8 HSSI Read Data[31:0] dyn_rcfg_dr_rx_src_alarm_reg Values
get_hssi_profile HSSI Write Data[31:24] = 9 HSSI Read Data[31:0] dyn_rcfg_local_error_stat_ctrl_reg Values
get_hssi_profile HSSI Write Data[31:24] = A HSSI Read Data[31:0] dyn_rcfg_local_rx_src_alarm_reg Values
Level Two Title