220.127.116.11. NOP(0x0) 18.104.22.168. get_hssi_profile for E-Tile 22.214.171.124. get_hssi_profile for F-Tile 126.96.36.199. set_hssi_profile for E-Tile 188.8.131.52. set_hssi_profile for F-Tile 184.108.40.206. read_MAC_statistic 220.127.116.11. get_mtu 18.104.22.168. set_csr for E-Tile 22.214.171.124. set_csr for F-Tile 126.96.36.199. get_csr for E-Tile 188.8.131.52. get_csr for F-Tile 184.108.40.206. enable_loopback for E-Tile 220.127.116.11. enable_loopback for F-Tile 18.104.22.168. disable_loopback for E-Tile 22.214.171.124. disable_loopback for F-Tile 126.96.36.199. Reset MAC Statistics 188.8.131.52. set_mtu for F-Tile 184.108.40.206. Ncsi_get_link_status 220.127.116.11. Reserved 18.104.22.168. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status
6.4. Clock Connections for SyncE Operation on E-Tile
The following figure shows an alternate clocking arrangement for the transceiver clocks that can be used to enable SyncE operation on E-Tile.
Figure 13. Alternate Clock Connections for SyncE Operation on E-Tile
From the figure, it is important to note:
- Two or more ports can share the clock output of an Off-chip Cleanup PLL that meets the specification for a SyncE link.
- The FPGA provides a Primary SyncE clock and a backup SyncE clock to the cleanup PLL.
- The Primary and backup cleanup clocks come from recovered clock output pins from a pair of ports that are both connected to remote stations connected to the same SyncE network, with the transceiver reference clock sourced from the output of the cleanup PLL.
- In the above figure, o_p<n>_clk_rec_div64 is used; o_p<n>_clk_rec_div can also be used.
- You must note if the EHIP System clock is derived from a different reference clock than the transceiver, then the IP must be set to Custom Cadence mode to match the PPM difference between the clocks.
- SyncE clocking can be combined with the datapath clocking schemes shown in the previous sections.
Note: The Ethernet ports do not have to be part of the same instance of the core, or variant.