7.3. F-Tile Address Maps
Base Address | Block | End Address |
---|---|---|
Subsystem | ||
0x000_0000 | Subsystem CSR | 0x000_FFFF |
0x001_0000 | ANLT | 0x0001_4FFF |
0x002_0000 | PTP Tile Adapter | 0x0005_FFFF |
Port 0 | (Quad 0 FGT 0, Port 00) | |
0x020_0000 | EHIP – Ethernet Reconfiguration | 0x020_FFFF |
0x026_1000 | PTP Packet Classifier | 0x026_11FF |
Port 1 | (Quad 0 FGT 1) | |
0x040_0000 | EHIP – Ethernet Reconfiguration |
0x040_FFFF |
0x046_1000 | PTP Packet Classifier | 0x046_11FF |
Port 2 | (Quad 0 FGT 2) | |
0x060_0000 | EHIP – Ethernet Reconfiguration | 0x060_FFFF |
0x066_1000 | PTP Packet Classifier | 0x066_11FF |
Port 3 | (Quad 0 FGT 3) | |
0x080_0000 | EHIP – Ethernet Reconfiguration | 0x080_FFFF |
0x086_1000 | PTP Packet Classifier | 0x086_11FF |
Port 4 | (Quad 1 FGT 0) | |
0x0A0_0000 | EHIP – Ethernet Reconfiguration | 0x0A0_FFFF |
0x0A6_1000 | PTP Packet Classifier | 0x0A6_11FF |
Port 5 | (Quad 1 FGT 1) | |
0x0C0_0000 | EHIP – Ethernet Reconfiguration | 0x0C0_FFFF |
0x0C6_1000 | PTP Packet Classifier | 0x0C6_11FF |
Port 6 | (Quad 1 FGT 2) | |
0x0E0_0000 | EHIP – Ethernet Reconfiguration | 0x0E0_FFFF |
0x0E6_1000 | PTP Packet Classifier | 0x0E6_11FF |
Port 7 | (Quad 1 FGT 3) | |
0x100_0000 | EHIP – Ethernet Reconfiguration | 0x100_FFFF |
0x106_1000 | PTP Packet Classifier | 0x106_11FF |
Port 8 | (Quad 2 FGT 0) | |
0x120_0000 | EHIP – Ethernet Reconfiguration | 0x120_FFFF |
0x126_1000 | PTP Packet Classifier | 0x126_11FF |
Port 9 | (Quad 2 FGT 1) | |
0x140_0000 | EHIP – Ethernet Reconfiguration | 0x140_FFFF |
0x146_1000 | PTP Packet Classifier | 0x146_11FF |
Port 10 | (Quad 2 FGT 2) | |
0x160_0000 | EHIP – Ethernet Reconfiguration | 0x160_FFFF |
0x166_1000 | PTP Packet Classifier | 0x166_11FF |
Port 11 | (Quad 2 FGT 3) | |
0x180_0000 | EHIP – Ethernet Reconfiguration | 0x180_FFFF |
0x186_1000 | PTP Packet Classifier | 0x186_11FF |
Port 12 | (Quad 3 FGT 0) | |
0x1A0_0000 | EHIP – Ethernet Reconfiguration | 0x1A0_FFFF |
0x1A6_1000 | PTP Packet Classifier | 0x1A6_11FF |
Port 13 | (Quad 3 FGT 1) | |
0x1C0_0000 | EHIP – Ethernet Reconfiguration | 0x1C0_FFFF |
0x1C6_1000 | PTP Packet Classifier | 0x1C6_110FF |
Port 14 | (Quad 3 FGT 2) | |
0x1E0_0000 | EHIP – Ethernet Reconfiguration | 0x1E0_FFFF |
0x1E6_1000 | PTP Packet Classifier | 0x1E6_11FF |
Port 15 | (Quad 3 FGT 3) | |
0x200_0000 | EHIP – Ethernet Reconfiguration | 0x200_FFFF |
0x206_1000 | PTP Packet Classifier | 0x206_11FF |
Port 16 | ( FHT 0) | |
0x220_0000 | EHIP – Ethernet Reconfiguration | 0x220_FFFF |
0x226_1000 | PTP Packet Classifier | 0x226_11FF |
Port 17 | ( FHT 1) | |
0x240_0000 | EHIP – Ethernet Reconfiguration | 0x240_FFFF |
0x246_1000 | PTP Packet Classifier | 0x246_11FF |
Port 18 | ( FHT 2) | |
0x260_0000 | EHIP – Ethernet Reconfiguration | 0x260_FFFF |
0x266_1000 | PTP Packet Classifier | 0x266_11FF |
Port 19 | ( FHT 3) | |
0x280_0000 | EHIP – Ethernet Reconfiguration | 0x280_FFFF |
0x286_1000 | PTP Packet Classifier | 0x286_11FF |
Base Address | Block | End Address |
---|---|---|
Channel 0 | (Quad 0 FGT 0, Port 00) | |
0x030_0000 | PHY – XCVR Reconfiguration | 0x03F_FFFF |
Channel 1 | (Quad 0 FGT 1) | |
0x050_0000 | PHY – XCVR Reconfiguration | 0x05F_FFFF |
Channel 2 | (Quad 0 FGT 2) | |
0x070_0000 | PHY – XCVR Reconfiguration | 0x07F_FFFF |
Channel 3 | (Quad 0 FGT 3) | |
0x090_0000 | PHY – XCVR Reconfiguration | 0x09F_FFFF |
Channel 4 | (Quad 1 FGT 0) | |
0x0B0_0000 | PHY – XCVR Reconfiguration | 0x0BF_FFFF |
Channel 5 | (Quad 1 FGT 1) | |
0x0D0_0000 | PHY – XCVR Reconfiguration | 0x0DF_FFFF |
Channel 6 | (Quad 1 FGT 2) | |
0x0F0_0000 | PHY – XCVR Reconfiguration | 0x0FF_FFFF |
Channel 7 | (Quad 1 FGT 3) | |
0x110_0000 | PHY – XCVR Reconfiguration | 0x11F_FFFF |
Channel 8 | (Quad 2 FGT 0) | |
0x130_0000 | PHY – XCVR Reconfiguration | 0x13F_FFFF |
Channel 9 | (Quad 2 FGT 1) | |
0x150_0000 | PHY – XCVR Reconfiguration | 0x15F_FFFF |
Channel 10 | (Quad 2 FGT 2) | |
0x170_0000 | PHY – XCVR Reconfiguration | 0x17F_FFFF |
Channel 11 | (Quad 2 FGT 3) | |
0x190_0000 | PHY – XCVR Reconfiguration | 0x19F_FFFF |
Channel 12 | (Quad 3 FGT 0) | |
0x1B0_0000 | PHY – XCVR Reconfiguration | 0x1BF_FFFF |
Channel 13 | (Quad 3 FGT 1) | |
0x1D0_0000 | PHY – XCVR Reconfiguration | 0x1DF_FFFF |
Channel 14 | (Quad 3 FGT 2) | |
0x1F0_0000 | PHY – XCVR Reconfiguration | 0x1FF_FFFF |
Channel 15 | (Quad 3 FGT 3) | |
0x210_0000 | PHY – XCVR Reconfiguration | 0x21F_FFFF |
Channel 16 | ( FHT 0) | |
0x230_0000 | PHY – XCVR Reconfiguration | 0x23F_FFFF |
Channel 17 | ( FHT 1) | |
0x250_0000 | PHY – XCVR Reconfiguration | 0x25F_FFFF |
Channel 18 | ( FHT 2) | |
0x270_0000 | PHY – XCVR Reconfiguration | 0x27F_FFFF |
Channel 19 | ( FHT 3) | |
0x290_0000 | PHY – XCVR Reconfiguration | 0x29F_FFFF |
Register Type | Address Range |
---|---|
F-Tile AIB Config | 0x0000 – 0x00FC |
Soft CSRs | 0x0100 – 0x0FFC |
EHIP Registers | 0x1000 – 0x5FFC |
FEC/XCVRIF Registers | 0x6000 – 0x9FFC |
The Ethernet Reconfiguration interface provides access to the EHIP Avalon® memory-mapped address space for the local EHIP fracture, including MAC, PCS, FEC and XCVRIF, as well as soft CSRs implemented in the FPGA fabric. The layout of this register space is described in more detail in the F-tile Hard IP for Ethernet User Guide. All addresses in this section are byte addresses, although the registers described are always accessed on 32-bit boundaries.
The EHIP and FEC/XCVRIF Registers spaces are mapped differently for different ethernet modes (10g/25g, 50g, 40g/100g, 200g, 400g) and are described in the F-tile Hard IP for Ethernet User Guide.
Ethernet Mode | eth_reconfig Base Address |
---|---|
10g/25g | 0x1000 |
50g | 0x2000 |
40g/100g | 0x3000 |
200g | 0x4000 |
400g | 0x5000 |
The following table shows the F-tile CSR address (Section 8 in F-Tile Ethernet Intel® FPGA Hard IP User Guide) mapping for channel 0/Quad 0 FGT 0. The CSR address mapping for different channels share the same byte offset. For example, channel 0 base address starts at 0x020_0000, and channel 8 base address is 0x120_0000. You can directly add the CSR byte offset address with base address of the channel to obtain the CSR address on particular channel. The CSR address is in byte offset, so the offset is directly added to base address without multiplication. To access this register, you must write bits 2-25 of this calculated address to the HSSI Control/Address CSR with the set_csr SAL command.
Base Address | Byte Offset | Descriptions | Configuration |
---|---|---|---|
Channel 0 | (Quad 0 FGT 0) | - | |
0x020_0000 (EHIP – Ethernet Reconfiguration) | 0x0000 – 0x00FC | F-Tile AIB Config | - |
0x0100 – 0x0FFC | Soft CSRs | ||
0x1000 (10GE/25GE) | 0x000-0x07C | PCS Configuration | |
0x080-0x1FC | PCS Status | ||
0x200-0x7FC | MAC/PTP Configuration | ||
0x800-0xFFC | MAC/PTP Statistics | ||
0x2000 (50GE) | Same as above | Same as above | |
0x3000 (40GE/100GE) | Same as above | Same as above | |
0x4000 (200GE) | Same as above | Same as above | |
0x5000 (400GE) | Same as above | Same as above | |
0x020_0000 (FEC/XCVR – Ethernet Reconfiguration) | eth_reconfig Base Address | Offset Address | FEC/XCVRIF Lane Segment |
0x6000 (25g) | 0x000 - 0x0BC (Transceiver Interface Control ) | segment 0 | |
0x0C0 - 0x0FC (FEC Configuration ) | |||
0x100 - 0x13C (Transceiver Status) | |||
0x140 - 0x1FC (FEC Status ) | |||
0x6200 (50g) | Same as above | segment 0 | |
0x6400 (50g) | Same as above | segment 1 | |
0x6600 (100g) | Same as above | segment 0 | |
0x6800 (100g) | Same as above | segment 1 | |
0x6A00 (100g) | Same as above | segment 2 | |
0x6C00 (100g) | Same as above | segment 3 | |
0x6E00 (200g) | Same as above | segment 0 | |
0x7000 (200g) | Same as above | segment 1 | |
0x7200 (200g) | Same as above | segment 2 | |
0x7400 (200g) | Same as above | segment 3 | |
0x7600 (200g) | Same as above | segment 4 | |
0x7800 (200g) | Same as above | segment 5 | |
0x7A00 (200g) | Same as above | segment 6 | |
0x7C00 (200g) | Same as above | segment 7 | |
0x7E00 (400g) | Same as above | segment 0 | |
0x8000 (400g) | Same as above | segment 1 | |
0x8200 (400g) | Same as above | segment 2 | |
0x8400 (400g) | Same as above | segment 3 | |
0x8600 (400g) | Same as above | segment 4 | |
0x8800 (400g) | Same as above | segment 5 | |
0x8A00 (400g) | Same as above | segment 6 | |
0x8C00 (400g) | Same as above | segment 7 | |
0x8E00 (400g) | Same as above | segment 8 | |
0x9000 (400g) | Same as above | segment 9 | |
0x9200 (400g) | Same as above | segment 10 | |
0x9400 (400g) | Same as above | segment 11 | |
0x9600 (400g) | Same as above | segment 12 | |
0x9800 (400g) | Same as above | segment 13 | |
0x9A00 (400g) | Same as above | segment 14 | |
0x9C00 (400g) | Same as above | segment 15 | |
0x020_A000 (Reserved) | - | Reserved | - |
0x021_1000 (PTP Packet Classifier) | - | PTP Packet Classifier | - |
0x024_0000 (PHY – XCVR Reconfiguration) | - | PHY – XCVR Reconfiguration | - |
The following example shows CSR access decoding.
Assuming you would like to access Tx MAC Link Fault Config register (For details, refer to F-tile Hard IP for Ethernet Register Map) for Agilex F-tile channel 8.
Tx MAC Link Fault Config register byte offset = 0x1200
F-tile transceiver channel 8 base address = 0x1200000
AXI-Lite CSR read request address = 0x405*4 + 0x1200000 = 0x1201014 (byte addressing)
This request will be decoded and routed to Ethernet Reconfiguration interface for processing.
Ethernet Mode | FEC/XCVRIF Lane Segment | eth_reconfig Base Address |
---|---|---|
25g | s0 | 0x6000 |
50g | s0 | 0x6200 |
s1 | 0x6400 | |
100g | s0 | 0x6600 |
s1 | 0x6800 | |
s2 | 0x6A00 | |
s3 | 0x6C00 | |
200g | s0 | 0x6E00 |
s1 | 0x7000 | |
s2 | 0x7200 | |
s3 | 0x7400 | |
s4 | 0x7600 | |
s5 | 0x7800 | |
s6 | 0x7A00 | |
s7 | 0x7C00 | |
400g | s0 | 0x7E00 |
s1 | 0x8000 | |
s2 | 0x8200 | |
s3 | 0x8400 | |
s4 | 0x8600 | |
s5 | 0x8800 | |
s6 | 0x8A00 | |
s7 | 0x8C00 | |
s8 | 0x8E00 | |
s9 | 0x9000 | |
s10 | 0x9200 | |
s11 | 0x9400 | |
s12 | 0x9600 | |
s13 | 0x9800 | |
s14 | 0x9A00 | |
s15 | 0x9C00 |