Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 8/29/2023

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Document Table of Contents
Give Feedback set_csr for E-Tile

set_csr SAL command is an indirect CSR access to write to registers of the Ethernet Subsystem. The CSR address and write data are written into the HSSI Control/Address Register and the Write Data Register respectively. Then, a write to the HSSI Command/Status CSR is required to trigger the write CSR operation.

For base addresses, refer to Register Descriptions.

For register map of E-tile Hard IP for Ethernet Hard IP, refer to Port Registers.

The table below shows the E-tile CSR address mapping (Refer to the Register Description of E-Tile Ethernet Hard IP User Guide) for channel 0. Except for the difference in base address, which is specified in the Register Map section, the CSR address mapping for different channels have the same word/byte offset as indicated in the table below. For example, channel 0's base address is 0x020_0000, while channel 8 base address is 0x120_0000. You need to multiply the register address in word offset by four then add the base address of the channel to obtain the CSR address on that channel. If the CSR address is in byte offset (for example PTP registers), the offset is directly added to base address without multiplication. To access these registers, use the set_csr SAL command to write bit [25:2] of the calculated address to the HSSI Control/Address Register.
Table 25.  E-Tile CSR Address
Base Address Word/Byte Offset Description
Channel 0
0x020_0000 (EHIPLANE/EHIPCORE – Ethernet Reconfiguration) (Word offset) 0x0B0-0x0E8 Auto Negotiation and Link Training registers
0x300-0x3FF PHY registers
0x310-0x310 Reset Controller registers (E-Tile)
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x7FF Pause and Priority- Based Flow Control registers
0x800-0x8FF TX Statistics Counter registers
0x900-0x9FF RX Statistics Counter registers
0xA00-0xAFF TX 1588 PTP registers
0xB00-0xBFF RX 1588 PTP registers
0x020_4000 (RS-FEC – RS-FEC Reconfiguration) (Byte offset) 0x000-0x2FF TX and RX RS-FEC registers
0x024_0000 (PHY – XCVR Reconfiguration) (Byte offset) 0x000-0x144 PMA Capability registers (0x40000-0x40144)
0x025_0000 (PHY – XCVR Reconfiguration) (Byte offset) 0x000-0x207 PMA AVMM registers
0x026_0000 N/A Soft IPs (MAC, PCS)
0x026_1000 (Byte offset) Parser registers offset (Byte offset) PTP Packet Classifier
0x026_2000 Reserved

The following example shows how the Address[25:2] field in the HSSI Control/Address CSR is determined (Please refer to the specific Ethernet User Guide for a detailed register map).

TX MAC Link Fault Configuration register word offset = 0x405

The E-Tile transceiver channel 8 base address = 0x1200000 (Refer to the base address of each E-tile channel).

AXI-Lite CSR read request address = 0x405*4 + 0x120_0000 = 0x120_1014 (byte addressing).

PTP Packet Classifier Registers use the same access mechanism as Ethernet Reconfiguration Registers.

The following example illustrates a user accessing the RS-FEC rsfec_top_tx_cfg register (For the detailed register address map, refer to the E-Tile Transceiver User Guide) for E-Tile channel 10.
  • rsfec_top_tx_cfg register byte offset = 0x10
  • The E-Tile transceiver channel 10 base address = 0x160_4000
  • AXI-Lite CSR write request address = 0x160_4000 + 0x10 = 0x160_4010 (depending on write strobe, a single AX-Lite write can create up to four single-byte write access.
  • AXI-Lite CSR write request address = 0x160_4000 + 0x10 = 0x160_4010 (depending on write strobe, a single AX-Lite write can create up to four single-byte write access.
  • AXI-Lite CSR read request address = 0x160_4000 + 0x10 = 0x160_4010 (a single AXI-Lite read can generate four single byte read accesses to the RS-FEC reconfiguration interface. For example, read 1B from 0x160_4010, read 1B from 0x160_4011, read 1B from 0x160_4012, read 1B from 0x160_4013, and return all 32b through AXI-Lite in single request.
  • HSSI Control/Address CSR Address[25:2] field = 0x160_4010 / 4 = 0x58100.
  • PMA AVMM and capability registers use the same access mechanism as RS-FEC registers. These registers will be internally routed to XCVR Reconfiguration interface or PTP XCVR Reconfiguration interface depending on the channel number.