7.1.10. HSSI Command/Status
Description: HSSI Command/Status
Byte Offset: 0xA8
Addressing Mode: 32 bits
Register Offset (Applicable only on E-tile)
Specify the 8b register offset for PMA AVMM/Capabilities register read/write through get_csr and set_csr SAL command
CSR address = Address[25:2] (HSSI Control/Address) + Address[1:0] (Register Offset)
1'b1 - Indicate SAL command timeout after 10ms and not completed successfully. User can resubmit the SAL command after root causing the error.
1'b0 - Indicate SAL command execute successfully without error
Valid when ACK_TRANS is asserted
1'b1 - Indicate SAL is in the middle of processing a command. Software should not send in new command when this bit is asserted.
1'b0 - Indicate SAL is free to accept new command.
|2:2||RW||0||ACK_TRANS: Bit gets asserted when transaction is complete. Must be cleared when asserted.|