Visible to Intel only — GUID: xia1669135761883
Ixiasoft
4.3.1.1. NOP(0x0)
4.3.1.2. get_hssi_profile for E-Tile
4.3.1.3. get_hssi_profile for F-Tile
4.3.1.4. set_hssi_profile for E-Tile
4.3.1.5. set_hssi_profile for F-Tile
4.3.1.6. read_MAC_statistic
4.3.1.7. get_mtu
4.3.1.8. set_csr for E-Tile
4.3.1.9. set_csr for F-Tile
4.3.1.10. get_csr for E-Tile
4.3.1.11. get_csr for F-Tile
4.3.1.12. enable_loopback for E-Tile
4.3.1.13. enable_loopback for F-Tile
4.3.1.14. disable_loopback for E-Tile
4.3.1.15. disable_loopback for F-Tile
4.3.1.16. Reset MAC Statistics
4.3.1.17. set_mtu for F-Tile
4.3.1.18. Ncsi_get_link_status
4.3.1.19. Reserved
4.3.1.20. firmware_version (0xFF)
6.1. Driving Multiple Ports with the Same Clock
6.2. Clock Connections for MAC Async Client FIFO
6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases
6.4. Clock Connections for SyncE Operation on E-Tile
6.5. Clock Connections for SyncE Operation on F-Tile
6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7.1.1. Device Feature Header Lo
7.1.2. Device Feature Header Hi
7.1.3. Feature GUID_L
7.1.4. Feature GUID_H
7.1.5. Feature CSR ADDR
7.1.6. Feature CSR Size Group
7.1.7. Version
7.1.8. Feature List
7.1.9. Interface Attribute Port X Parameters
7.1.10. HSSI Command/Status
7.1.11. HSSI Control/Address
7.1.12. HSSI Read Data
7.1.13. HSSI Write Data
7.1.14. HSSI Ethernet Port X Status
Visible to Intel only — GUID: xia1669135761883
Ixiasoft
7.5. F-Tile PTP Tile Adapter Register Map
The PTP Tile Adapter CSRs are mapped to the subsystem CSR space.
Reconfiguration Interface | Address |
---|---|
PTP Asymmetry | Byte Offset: 0x20000 - 0x3FFFF |
PTP Peer-to-Peer MeanPathDelay | Byte Offset: 0x40000 - 0x5FFFF |