Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 8/29/2023

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Give Feedback Steps to generate Routing Delay for PTP Enabled Designs

You need to generate the routing delay, if you have created a PTP design example with Advanced Timestamp Accuracy Mode in F-Tile.

  1. After successful compilation, navigate to <Design Example >/hardware_test_design directory.
  2. Copy <design example>/ex_ss/eth_f_<version>/synth/eth_f_ptp_report_dl_path_delay.tcl to the current directory.

    Run the script: quartus_sta -t eth_f_ptp_report_dl_path_delay.tcl <project_name>. The main script sources the generated ptp_hw_adv_adj.tcl for routing delay adjustment.

  3. Update the script with the loopback module's delay. This is an optional step if timestamp accuracy is not a concern.
    1. Open the <design_example>/hardware_test_design/hwtest_f/altera/ptp/ptp_params.tcl file.
    2. Locate set PHY_DLY command based on the <xcvr_type> transceiver type and the <apl> physical lane number. For example, the following line specifies the channel placed at the top-most FGT lane: set PHY_DLY(lpbk_module_dly,0,15).
    3. Modify the <delay_value> of loopback module channel. The default value is set to 0.
    4. Repeat steps b and c for all of the active channels.
    Note: The tx_board_dly and rx__board_dly values provided in the ptp params.tcl file are specific to the selected development kit. you must update these values, if you are running the script on a different board.