Ethernet Subsystem Intel® FPGA IP User Guide

ID 773413
Date 8/29/2023
Public

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7.1.8. Feature List

Description: Feature List

Byte Offset: 0x64

Addressing Mode: 32 bits

Bit Type Value after Reset Description
31:26 for F-Tile

31:22 for E-Tile

RO 0 Reserved

25:6 for F-Tile

21:6 for E-Tile

RO 0

Physical Port Enable

  • [6]-Port 0 enable
  • [7]-Port 1 enable
  • [8]-Port 2 enable
  • [9]-Port 3 enable
  • [10]-Port 4 enable
  • [11]-Port 5 enable
  • [12]-Port 6 enable
  • [13]-Port 7 enable
  • [14]-Port 8 enable
  • [15]-Port 9 enable
  • [16]-Port 10 enable
  • [17]-Port 11 enable
  • [18]-Port 12 enable
  • [19]-Port 13 enable
  • [20]-Port 14 enable
  • [21]-Port 15 enable
  • [22]-Port 16 Enable (F-Tile Only)
  • [23]-Port 17 Enable (F-Tile Only)
  • [24]-Port 18 Enable (F-Tile Only)
  • [25]-Port 19 Enable (F-Tile Only)
5:1 RO 0 Number of HSSI Ports Instantiated (NUM_ENABLED_PORTS parameter)
0:0 RO 1 AXI-4 support