MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

7. MACsec Intel® FPGA IP Example Design

The block diagram below shows the MACsec IP design example.
Figure 31. MACsec IP Design Example

The IP GUI can generate (5) individual design examples. The design example GUI is updated to only support working examples. In order to generate one of the variants below, please select the following options for your project and IP parameter settings.

Table 57.  Available MACsec Design Example Variant
Design Number of TX Ports Number of TX + RX Ports Port Data Width Maximum Crypto Channels
1x25G 1 2 64 16
4x25G 4 8 64 64
1x100G 1 2 256 16