MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

7.4. Multi Interface Buffering Muxing/Demuxing

The diagram below illustrates the Multi Interface Buffering Mux/Demux block diagram. The MACsec User Interface is capable of supporting a maximum of 32 AXI-ST ports in both Tx and Rx directions. Each AXI-ST port goes through the programmable pipeline logic within the block. Depending on the connections of the user interface at the system Level, each port can support either encryption, decryption or bypass operation.

Figure 33. Multi Interface Buffering Muxing/Demuxing