MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

6. Configuration Registers for MACsec IP

You access the configuration and status registers for the MACsec Intel FPGA IP using the AXI_lite Management interface. These registers use 25-bit addresses.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have an undefined effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variant, have an unspecified result. You should consider these registers and register bits as Reserved.

For more information about specific Management interface address register descriptions, refer to MACsec Intel FPGA Hard IP Register Map.