MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

5.8.2. Memory Blocks ECC Errors

The Intel Agilex™ 7 FIFO Intel FPGA IP cores support embedded memory ECC for M20K memory blocks. The built-in ECC feature in the Agilex™ 7 devices can perform:
  • Single-error detection and correction
  • Double-adjacent-error detection and correction
  • Triple-adjacent-error detection
Upon detection of ECC errors, the 2 bits ECC status bits are logged into the Error CSR. ECC status bits from all memory blocks are combined into the Error CSR register [1:0] and an interrupt signal is asserted. The priority of ECC error logging follows the encodings below from top to bottom.
  • 11: An uncorrectable error occurs and uncorrectable data appears at the output.
  • 10: A correctable error occurs and the error is corrected at the outputs; however, the memory array is not updated.
  • 01: Illegal
  • 00: No error