MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

7.3. Port Configurations

The MACsec ED user interface supports a maximum of 4 AXI-ST input and output ports. The number of ports is configured during IP generation time through Quartus GUI as shown in Available MACsec Design Example Variant. The bandwidth supported by the MACsec IP is 200Gbps and therefore the aggregated bandwidth of all ports should not exceed 200Gbps. In the scenario where the desired bandwidth exceeds the port bandwidth, backpressure occurs to avoid a buffer overflow.

The number of input ports always match the number of output ports. Traffic entering the MACsec IP input port leaves the IP output port with the same index. For example, traffic entering input port 0 leaves at output port 0.

The AXI-ST TID is used to indicate the Port ID and this ID is tagged along with the packet flowing through the MACsec lane to identify the destination output Controlled port or Common port. The AXI-ST TID value is fixed in a Multi Interface Buffering Mux/Demux based on the MAX TX TID parameter value. The MUX/DEMUX is always in store-forward mode while it is being assigned. For example, in a 2 Tx port 2 Rx port configuration, TID 0 and 1 are assigned internally to Tx port 0 and port 1, while TID 2 and 3 are assigned internally to Rx port 0 and port 1. It is not necessary to assign any value to the AXI-ST TID signal when sending the request into the Multi Interface Buffering Mux/Demux. Refer to Port and Crypto Channel Mapping for some examples of how TID is assigned based on the MAX TX TID parameter.

For F-tile Ethernet Hard IP, the default value of maximum packet size is set to 1518. In order to match the maximum packet size between Ethernet and MACsec, MAX_TX_SIZE_CONFIG and MAX_RX_SIZE_CONFIG CSRs in the Ethernet Hard IP are required to be configured to 9600.