MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

4.2. Specifying the IP Core Parameters and Options

The IP parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Quartus® Prime Pro Edition software.

  1. If you do not already have an Quartus® Prime Pro Edition project in which to integrate your Symmetric Cryptographic Intel® FPGA Hard IP core, you must create one.
    1. In the Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Quartus Prime project, or File > Open Project to open an existing Quartus Prime project. The wizard prompts you to specify a device.
    2. Specify the device family Agilex™ 7 and select a device that contains the Symmetric Cryptographic Intel® FPGA Hard IP that meets the speed grade requirements for the IP core.
    3. Click Finish.
  2. In the IP Catalog, locate and select MACsec Intel® FPGA IP. The New IP Variation window appears.
  3. Specify a top-level name for your new custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. Specify the parameters for your IP core variation. Refer to MACsec Intel FPGA IP Parameter Settings for information about specific IP core parameters.
  6. Optionally, to generate a simulation testbench or compilation and hardware design example, follow the instructions in the MACsec Intel FPGA IP Example Design.
  7. Click Generate HDL. The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  9. Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.