MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

5.3.3. New Channel Assignment

The Crypto AES block requires channel allocation at the beginning of a new MACsec flow. Keys and IV are expected to be sent to the Crypto AES engine before the payload is sent. When an SA entry is first allocated into SADB, the channel_in-use CSR bit is expected to be reset to 0.

The initial SA lookup that hits the SA entry observes this bit set to 0 and this bit is sent to the Encryption/Decryption Framer/Deframer to initiate a channel allocation cycle before a payload is sent to Crypto AES.

The channel_in-use CSR bit for this SA entry is then set to 1 to indicate the channel allocation is done and the SA update is scheduled to SADB.