MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents SmartNIC

In a typical SmartNIC application, the flow of data is as shown below:

PCIe (Host) > PCIe (FPGA) > Packet Processing Blocks > MACsec IP (FPGA) > User Logic > Transceiver (QSFP28)

The figure below shows the location of the MACsec IP within a SmartNIC system. The bandwidth which could be achieved with such a system is 200Gbps.

You can use the MACsec IP to encrypt or decrypt L2 packets in a SmartNIC use case. In this use case, you can offload the transmitting packets from the host through the PCIe link. The packet processing logic parses the incoming packets and performs functions such as routing, network address translation, telemetry, and load balancing. Then, those packets that require encryption are routed to the MACsec IP, and finally, the MACsec IP sends out the encrypted packet through the Ethernet port to the destination.

Figure 1. SmartNIC