MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

5.1.1. AXI-ST Single Packet Mode

The AXI-ST Single Packet Mode is supported on all user interface input and output ports. The AXI specification defines the Single Packet Mode where at any one clock, there can only be one transaction in progress. The waveform below shows the example for AXI4-Streaming case and there can only be one Request or Response respectively.

Figure 20. Single Packet Mode