MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

5.7.1. Register Address Ordering

The MACsec IP supports the AXI-Lite protocol for configuring its registers, with data bus width up to 64 bits. The MACsec IP uses little endian byte order for IV/key/data. For register address ordering, for example, SALT registers are of 96-bit width. If hypothetically a SALT register has a starting address of 16’h1000, then:
  • Address 16’h1000 is for SALT[31:0]
  • Address 16’h1004 is for SALT[63:32]
  • Address 16’h1008 is for SALT[95:64]
For example, an SCI value 0x12153524C0895E81 should be written to register TX_LANE_SC<sc_index>_SCI at address <addr> with single configuration writes:
  • <addr> : 0xC0895E81
  • <addr> + 4 : 0x12153524

where TX_LANE_SC<sc_index>_SCI[63:56] = 0x12. All other CSRs are following the above address ordering except the key CSR.

For registers TX_LANE_SC<sc_index>_SA<sa_index>_KEY and RX_LANE_SC<sc_index>_SA<sa_index>_KEY, program the 256-bit registers with the key value. If a 128-bit key is used, it should be in bits [255:128] of the corresponding 256-bit key register.

For example, a key value of 0xAD7A2BD03EAC835A6F620FDCB506B345, written to the register TX_LANE_SC0_SA0_KEY at address 0x7d0 should be written as follows:
  • 0x7d00 0xB506B345
  • 0x7d04 0x6F620FDC
  • 0x7d08 0x3EAC835A
  • 0x7d0c 0xAD7A2BD0
  • 0x7d10 0x00000000
  • 0x7d14 0x00000000
  • 0x7d18 0x00000000
  • 0x7d1c 0x00000000