MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Document Table of Contents

2.2.3. Clocks, Resets, and Interrupts

Table 20.  Clocks
Signal Name Type Clock
app_ip_st_clk Clock The input clock of the MACsec IP. It is expected to operate at 400MHz and synchronous to AXI-ST interface clocks.
Table 21.  Resets
Signal Name Direction Type Description
subsystem_cold_rst_n Input Reset

Active-low hard global reset

Resets the full MACsec IP core

subsystem_cold_rst_ack_n Output

Reset acknowledge

Acknowledge signal for subsystem_cold_rst_n. Active low

User should not deassert subsystem_cold_rst_n until subsystem_cold_rst_ack_n is asserted

app_ip_lite_areset_n Input Reset Active-low reset for the AXI-Lite management interface
app_ip_st_areset_n Input Reset Active-low reset for the AXI-ST streaming interfaces
Table 22.  Interrupts
Signal Name Direction Type Description
macsec_app_ip_intr Output Control Interrupt signal. Asserted when errors or predefined events occur in the MACsec IP. Synchronous to app_ip_lite_clk.