MACsec Intel® FPGA IP User Guide

ID 736108
Date 3/31/2024
Public
Document Table of Contents

7.5. 4x25 GbE (Encryption + Decryption)

The diagram below shows Multi Interface Buffering Mux/Demux logic that is configured to 4 Controlled/Common ports. Each port is expected to operate at 25G with 64 bits of data width. There are 4 sets of Multi Interface Buffering Mux/Demux logic within the ED, one on the encryption data path and the other on the decryption data path. On the encryption data path, a Packet Generator sends unencrypted packets on the user interface Rx port 0 of the Mux and encrypted packets are sent out on the user interface Tx port 0 of the Demux to the Ethernet IP.

Figure 34. 4x25 GbE (Encryption + Decryption)


These packets on the decryption data path are sent to the user interface Rx port 0 of Mux and packets are later sending out on user interface Tx port 0 back to Pattern Checker.