Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

1.1. Arria® V GZ Avalon-MM Interface for PCIe Datasheet

Arria® V GZ FPGAs include a configurable, hardened protocol stack for PCI Express that is compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express IP core using the Avalon® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe* protocol. For example, it handles all of the Transaction Layer Packet (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in soft logic. It is available in Platform Designer.

Figure 1.  Arria® V GZ PCIe Variant with Avalon-MM InterfaceThe following figure shows the high-level modules and connecting interfaces for this variant.
The following table shows the aggregate bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1, 5.0 giga-transfers per second for Gen2, and 8.0 giga‑transfers per second for Gen3. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. In contrast, Gen3 uses 128b/130b encoding which reduces the data throughput lost to encoding to about 1.5%.
Note: Intel® Cyclone® 10 GX support up to Gen2 x4 configurations.
Table 1.  PCI Express Data Throughput
Link Bandwidth in Gigabits Per Second (Gbps)
x1 x2 x4 x8

PCI Express Gen1 (2.5 Gbps)





PCI Express Gen2 (5.0 Gbps)





PCI Express Gen3 (8.0 Gbps)





Refer to AN 456: PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs.