Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

A.4.2. Avalon-MM-to-PCI Express Write Requests

The Avalon-MM bridge accepts Avalon-MM burst write requests with a burst size of up to 512 bytes at the Avalon-MM TX slave interface. The Avalon‑MM bridge converts the write requests to one or more PCI Express write packets with 32– or 64‑bit addresses based on the address translation configuration, the request address, and the maximum payload size.

The Avalon-MM write requests can start on any address in the range defined in the PCI Express address table parameters. The bridge splits incoming burst writes that cross a 4 KB boundary into at least two separate PCI Express packets. The bridge also considers the root complex requirement for maximum payload on the PCI Express side by further segmenting the packets if needed.

The bridge requires Avalon-MM write requests with a burst count of greater than one to adhere to the following byte enable rules:

  • The Avalon-MM byte enables must be asserted in the first qword of the burst.
  • All subsequent byte enables must be asserted until the deasserting byte enable.
  • The Avalon-MM byte enables may deassert, but only in the last qword of the burst.
Note: To improve PCI Express throughput, Intel recommends using an Avalon-MM burst master without any byte-enable restrictions.