Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

9.3. Recommended Reset Sequence to Avoid Link Training Issues

Successful link training can only occur after the FPGA is configured and the Transceiver Reconfiguration Controller IP Core has dynamically reconfigured SERDES analog settings to optimize signal quality. For designs using CvP, link training occurs after configuration of the I/O ring and Hard IP for PCI Express IP Core. Refer to Reset Sequence for Hard IP for PCI Express IP Core and Application Layer for a description of the key signals that control reset, control dynamic reconfiguration, and link training. Intel recommends separate control of reset signals for the Endpoint and Root Port. Successful reset sequence includes the following steps:

  1. Wait until the FPGA is configured as indicated by the assertion of CONFIG_DONE from the FPGA block controller.
  2. Deassert the mgmt_rst_reset input to the Transceiver Reconfiguration Controller IP Core.
  3. Wait for tx_cal_busy and rx_cal_busy SERDES outputs to be deasserted.
  4. Wait 1 ms after the assertion of CONFIG_DONE, then deassert the Endpoint reset.
  5. Wait approximately 100 ms, then deassert the Root Port reset.
  6. Deassert the reset output to the Application Layer.
Figure 46. Recommended Reset Sequence