Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

3.4.1. Device Capabilities

Table 13.  Capabilities Registers


Possible Values

Default Value


Maximum payload size

128 bytes

256 bytes

128 bytes

Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

Completion timeout range









Indicates device function support for the optional completion timeout programmability mechanism. This mechanism allows the system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

  • Range A: 50 us to 10 ms
  • Range B: 10 ms to 250 ms
  • Range C: 250 ms to 4 s
  • Range D: 4 s to 64 s

Bits are set to show timeout value ranges supported. The function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:

  • None—Completion timeout programming is not supported
  • 0001 Range A
  • 0010 Range B
  • 0011 Ranges A and B
  • 0110 Ranges B and C
  • 0111 Ranges A, B, and C
  • 1110 Ranges B, C and D
  • 1111 Ranges A, B, C, and D

All other values are reserved. Intel recommends that the completion timeout mechanism expire in no less than 10 ms.

Implement completion timeout disable



For Endpoints using PCI Express version 2.1 or 3.0, this option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device Control Register 2. The Application Layer logic must implement the actual completion timeout mechanism for the required ranges.