Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

A.1.1. Avalon-MM Interface

An Avalon‑MM interface connects the Application Layer and the Transaction Layer. The Avalon-MM interface implement the Avalon-MM protocol described in the Avalon Interface Specifications. Refer to this specification for information about the Avalon-MM protocol, including timing diagrams.

Avalon-MM slaves use byte addresses. A slave only accepts addresses that are a multiple of its data width. Consequently, the lowest 2 bits of 32-bit address must be zero. Byte enables allow partial word access. For example, a write of 2 bytes at address 2 would have 4’b1100 for the byte enables. For larger accesses, additional low-order bits are unused, as shown in the following table.

Table 70.  Avalon-MM Address Bits used for 32-, 64-, 128- and 256-Bit Data Widths
Data Width Address Bits Used Address Bits Set to 0 and Ignored
32 bits addr[31:2] addr[1:0]
64 bits addr[63:3] addr[2:0]
128 bits addr[63:4] addr[3:0]
256 bits addr[63:5] addr[4:0]