Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

8. Transceiver PHY IP Reconfiguration

As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and adaptive equalization (AEQ) to ensure correct operation. Intel’s Platform Designer example designs all include Transceiver Reconfiguration Controller and Intel PCIe Reconfig Driver IP cores that automatically perform these functions during the LTSSM equalization states.