Visible to Intel only — GUID: nik1410564996502
Ixiasoft
Visible to Intel only — GUID: nik1410564996502
Ixiasoft
8. Transceiver PHY IP Reconfiguration
As silicon progresses towards smaller process nodes, circuit performance is affected by variations due to process, voltage, and temperature (PVT). Consequently, Gen3 designs require offset cancellation and adaptive equalization (AEQ) to ensure correct operation. Intel’s Platform Designer example designs all include Transceiver Reconfiguration Controller and Intel PCIe Reconfig Driver IP cores that automatically perform these functions during the LTSSM equalization states.
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