Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

4.2. Bursting and Non-Bursting Avalon® -MM Module Signals

The Avalon® -MM Master module translates read and write TLPs received from the PCIe* link to Avalon® -MM transactions for connected slaves. You can enable up to six Avalon® -MM Master interfaces. One of the six Base Address Registers (BARs) define the base address for each master interface. This module allows other PCIe* components, including host software, to access the Avalon® -MM slaves connected in the Platform Designer.
Table 20.  Avalon-MM RX Master Interface Signals <n> = the BAR number, and can be 0, 1, 2, 3, 4, or 5.

Signal Name





Asserted by the core to request a write to an Avalon-MM slave.



The address of the Avalon-MM slave being accessed.



RX data being written to slave. <w> = 64 or 128 for the full-featured IP core. <w> = 32 for the completer-only IP core.



Dword enables for write data.

RXMBurstCount_<n>_o[6 or 5:0]

(available in burst mode only)


>The burst count, measured in qwords, of the RX write or read request. The width indicates the maximum data that can be requested. The maximum data in a burst is 512 bytes. This optional signal is available for BAR2 only when you turn on Enable burst capabilities for RXM BAR2 ports.



Asserted by the external Avalon-MM slave to hold data transfer.



Asserted by the core to request a read.



Read data returned from Avalon-MM slave in response to a read request. This data is sent to the IP core through the TX interface. <w> = 64 or 128 for the full-featured IP core. <w> = 32 for the completer-only IP core.



Asserted by the system interconnect fabric to indicate that the read data is valid.

RxmIrq_i[<m>:0], <m>< 16


Connect interrupts to the Avalon® -MM interface. These signals are only available for the Avalon® -MM when the CRA port is enabled. A rising edge triggers an MSI interrupt. The hard IP core converts this event to an MSI interrupt and sends it to the Root Port. The host reads the Interrupt Status register to retrieve the interrupt vector. Host software services the interrupt and notifies the target upon completion.

As many as 16 individual interrupt signals (<m>≤15). If RxmIrq_i[<m>:0] is asserted on consecutive cycles without the deassertion of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.

The following timing diagram illustrates the RX master port propagating requests to the Application Layer and also shows simultaneous read and write activities.

Figure 9. Simultaneous RXM Read and RXM Write