Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

5.8.1. Sending a Write TLP

The Application Layer performs the following sequence of Avalon-MM accesses to the CRA slave port to send a Memory Write Request:

  1. Write the first 32 bits of the TX TLP to RP_TX_REG0 at address 0x2000.
  2. Write the next 32 bits of the TX TLP to RP_TX_REG1 at address 0x2004.
  3. Write the RP_TX_CNTRL.SOP to 1’b1 (RP_TX_CNTRL is at address 0x2008) to push the first two dwords of the TLP into the Root Port TX FIFO.
  4. Repeat Steps 1 and 2. The second write to RP_TX_REG1 is required, even for three dword TLPs with aligned data.
  5. If the packet is complete, write RP_TX_CNTRL to 2’b10 to indicate the end of the packet. If the packet is not complete, write 2’b00 to RP_TX_CNTRL.
  6. Repeat this sequence to program a complete TLP.

When the programming of the TX TLP is complete, the Avalon® -MM bridge schedules the TLP with higher priority than TX TLPs coming from the TX slave port.