Visible to Intel only — GUID: nik1410564920940
Ixiasoft
Visible to Intel only — GUID: nik1410564920940
Ixiasoft
5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
The following table describes the Interrupt Status register for Endpoints. It records the status of all conditions that can cause an Avalon-MM interrupt to be asserted.
Bits |
Name |
Access |
Description |
---|---|---|---|
0 |
ERR_PCI_WRITE_FAILURE | RW1C |
When set to 1, indicates a PCI Express write failure. This bit can also be cleared by writing a 1 to the same bit in the Avalon MM to PCI Express Interrupt Status register. |
1 |
ERR_PCI_READ_FAILURE | RW1C |
When set to 1, indicates the failure of a PCI Express read. This bit can also be cleared by writing a 1 to the same bit in the Avalon MM to PCI Express Interrupt Status register. |
2 | TX_FIFO_EMPTY | RW1C | When set to 1, indicates that the TX buffer is empty. Application Layer logic can read this bit to determine if all of the TX buffer is empty before safely changing the translation address entries. This bit is available only for Legacy Endpoints. |
[15:2] |
Reserved |
— |
— |
[16] |
P2A_MAILBOX_INT0 | RW1C |
1 when the P2A_MAILBOX0 is written |
[17] |
P2A_MAILBOX_INT1 | RW1C |
1 when the P2A_MAILBOX1 is written |
[18] |
P2A_MAILBOX_INT2 | RW1C |
1 when the P2A_MAILBOX2 is written |
[19] |
P2A_MAILBOX_INT3 | RW1C |
1 when the P2A_MAILBOX3 is written |
[20] |
P2A_MAILBOX_INT4 | RW1C |
1 when the P2A_MAILBOX4 is written |
[21] |
P2A_MAILBOX_INT5 | RW1C |
1 when the P2A_MAILBOX5 is written |
[22] |
P2A_MAILBOX_INT6 | RW1C |
1 when the P2A_MAILBOX6 is written |
[23] |
P2A_MAILBOX_INT7 | RW1C |
1 when the P2A_MAILBOX7 is written |
[31:24] |
Reserved |
— |
— |
Bits |
Name |
Access |
Description |
---|---|---|---|
[31:24] | Reserved | N/A | Reserved |
[23] | P2A_MAILBOX_INT7 | RW1C | Set to a 1 when the P2A_MAILBOX7 is written to. |
[22] | P2A_MAILBOX_INT6 | RW1C | Set to a 1 when the P2A_MAILBOX6 |
[21] | P2A_MAILBOX_INT5 | RW1C | Set to a 1 when the P2A_MAILBOX5 |
[20] | P2A_MAILBOX_INT4 | RW1C | Set to a 1 when the P2A_MAILBOX4 |
[19] | P2A_MAILBOX_INT3 | RW1C | Set to a 1 when the P2A_MAILBOX3 |
[18] | P2A_MAILBOX_INT2 | RW1C | Set to a 1 when the P2A_MAILBOX2 |
[17] | P2A_MAILBOX_INT1 | RW1C | Set to a 1 when the P2A_MAILBOX1 |
[16] | P2A_MAILBOX_INT0 | RW1C | Set to a 1 when the P2A_MAILBOX0 |
[15:0] | Reserved | N/A | Reserved |
10:0 |
Root Port Interrupt | RW1C |
Interrupt status when bridge is in root complex mode. Since EB release does not support root mode, this register is not valid. [0] : INTA [1] : INTB [2] : INTC [3] : INTD [4] : RC AER error [5] : PME interrupt status [6] : hot plug event when PME is enabled [7] : hot plug event [8] : autonomous bandwidth [9] : bandwidth management [10] : link equalization request |
An Avalon-MM interrupt can be asserted for any of the conditions noted in the Avalon-MM Interrupt Status register by setting the corresponding bits in the PCI Express to Avalon-MM Interrupt Enable register.
PCI Express interrupts can also be enabled for all of the error conditions described. However, it is likely that only one of the Avalon-MM or PCI Express interrupts can be enabled for any given bit. Typically, a single process in either the PCI Express or Avalon-MM domain handles the condition reported by the interrupt.
Bits |
Name |
Access |
Description |
---|---|---|---|
[31:24] | Reserved | N/A | Reserved |
[23] | P2A_MAILBOX_INT7 | RW1C | Set to a 1 when the P2A_MAILBOX7 is written to. |
[22] | P2A_MAILBOX_INT6 | Set to a 1 when the P2A_MAILBOX6 | |
[21] | P2A_MAILBOX_INT5 | Set to a 1 when the P2A_MAILBOX5 | |
[20] | P2A_MAILBOX_INT4 | Set to a 1 when the P2A_MAILBOX4 | |
[19] | P2A_MAILBOX_INT3 | Set to a 1 when the P2A_MAILBOX3 | |
[18] | P2A_MAILBOX_INT2 | Set to a 1 when the P2A_MAILBOX2 | |
[17] | P2A_MAILBOX_INT1 | Set to a 1 when the P2A_MAILBOX1 | |
[16] | P2A_MAILBOX_INT0 | Set to a 1 when the P2A_MAILBOX0 | |
[15:0] | Reserved | N/A | Reserved |