Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

ID 723696
Date 5/21/2017
Document Table of Contents

A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge

The PCI Express Avalon‑MM bridge translates the system‑level physical addresses, typically up to 64 bits, to the significantly smaller addresses required by the Application Layer’s Avalon‑MM slave components.

Note: Starting with the 13.0 version of the Quartus® Prime software, the PCI Express‑to‑Avalon‑MM bridge supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform address translation. It drives the addresses specified to the interconnect fabric. You can limit the number of address bits used by Avalon-MM slave components to the actual size required by specifying the address size in the Avalon-MM slave component parameter editor.

You can specify up to six BARs for address translation when you customize your Hard IP for PCI Express as described in Base Address Register (BAR) and Expansion ROM Settings. When 32-bit addresses are specified, the PCI Express Avalon‑MM bridge also translates Application Layer addresses to system‑level physical addresses as described in Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing.

The following figure provides a high‑level view of address translation in both directions.

Figure 35. Address Translation in TX and RX Directions For Endpoints
Note: When configured as a Root Port, a single RX Avalon‑MM master forwards all RX TLPs to the Platform Designer interconnect.

The Avalon-MM RX master module port has an 8-byte datapath in 64‑bit mode and a 16‑byte datapath in 128‑bit mode. The Platform Designer interconnect fabric manages mismatched port widths transparently.

As Memory Request TLPs are received from the PCIe link, the most significant bits are used in the BAR matching as described in the PCI specifications. The least significant bits not used in the BAR match process are passed unchanged as the Avalon-MM address for that BAR's RX Master port.

For example, consider the following configuration specified using the Base Address Registers in the parameter editor:

  1. BAR1:0 is a 64-bit prefetchable memory that is 4KBytes -12 bits
  2. System software programs BAR1:0 to have a base address of 0x0000123456789000
  3. A TLP received with address 0x0000123456789870
  4. The upper 52 bits (0x0000123456789) are used in the BAR matching process, so this request matches.
  5. The lower 12 bits, 0x870, are passed through as the Avalon address on the Rxm_BAR0 Avalon-MM Master port. The BAR matching software replaces the upper 20 bits of the address with the Avalon‑MM base address.