AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents x
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families x
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview x
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices x
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example x
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis x
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

I/O Standards for BLVDS Interface in Intel FPGA Devices

You can implement the BLVDS interface using the relevant I/O standards and current strength requirements for the supported Intel® devices.
Table 2.  I/O Standard and Features Support for the BLVDS Interface in Supported Intel® Devices
Devices Pin I/O Standard V CCIO (V) Current Strength Option Slew Rate
Column I/O Row I/O Option Setting Intel® Quartus® Prime Setting
Intel® Stratix® 10 LVDS

Differential SSTL-18 Class I

 1.8 8, 6, 4 —— Slow 0
Fast (Default) 1
Differential SSTL-18 Class II 1.8 8 — Slow 0
Fast (Default) 1

Intel® Cyclone® 10 LP

Cyclone® IV

Cyclone® III

DIFFIO BLVDS 2.5 8, 12 (default), 16 8, 12 (default), 16 Slow 0
Medium 1
Fast (default) 2

Stratix® IV

Stratix® III

Arria® II

DIFFIO_RX 1 Differential SSTL-2 Class I 2.5 8, 10, 12 8, 12 Slow 0
Medium 1
Medium fast 2
Fast (default) 3
Differential SSTL-2 Class II 2.5 16 16 Slow 0
Medium 1
Medium fast 2
Fast (default) 3

Stratix® V

Arria® V

Cyclone® V

DIFFIO_RX 1 Differential SSTL-2 Class I 2.5 8, 10, 12 8, 12 Slow 0
Differential SSTL-2 Class II 2.5 16 16 Fast (default) 1

Intel® Arria® 10

Intel® Cyclone® 10 GX

LVDS Differential SSTL-18 Class I 1.8 4, 6, 8, 10, 12 — Slow 0
Differential SSTL-18 Class II 1.8 16 — Fast (default) 1
Intel® MAX® 10 DIFFIO_RX BLVDS 2.5 8, 12, 16 (default) 8, 12, 16 (default) Slow 0
Medium 1
Fast (default) 2

For more information, refer to the respective device documentation as listed in the related information section:

  • For pin assignments information, refer to the device pin-out files.
  • For the I/O standards features, refer to the device handbook I/O chapter.
  • For the electrical specifications, refer to the device datasheet or DC and switching characteristics document.
Related Information
1 DIFFIO_TX pin does not support true LVDS differential receivers.
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