AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018
Public

BLVDS Technology in Intel Devices

In supported Intel devices, the BLVDS interface is supported in any row or column I/O banks that are powered by a VCCIO of 1.8 V ( Intel® Arria® 10 and Intel® Cyclone® 10 GX devices) or 2.5 V (other supported devices). In these I/O banks, the interface is supported on the differential I/O pins but not on the dedicated clock input or clock output pins. However, in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the BLVDS interface is supported on dedicated clock pins that are used as general I/Os.
  • The BLVDS transmitter uses two single-ended output buffers with the second output buffer programmed as inverted.
  • The BLVDS receiver uses a dedicated LVDS input buffer.
Figure 4. BLVDS I/O Buffers in the Supported Devices


Use different input or output buffers depending on the application type:

  • Multidrop application—use the input or output buffer depending on whether the device is intended for driver or receiver operation.
  • Multipoint application—the output buffer and input buffer shares the same I/O pins. You require an output enable (oe) signal to tri-state the LVDS output buffer when it is not sending signals.
    • Do not enable the on-chip series termination (RS OCT) for the output buffer.
    • Use external resistors at the output buffers to provide impedance matching to the stub on the plug-in card.
    • Do not enable the on-chip differential termination (RD OCT) for the differential input buffer because the bus termination is usually implemented using the external termination resistors at both ends of the bus.

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