AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018
Public

Design Example Guidelines for Intel® Stratix® 10 Devices

These steps are applicable to Intel® Stratix® 10 devices only. Ensure that you use the GPIO Intel® FPGA IP core.
  1. Create an GPIO Intel® FPGA IP core that can support a bidirectional input and output buffer:
    1. Instantiate the GPIO Intel® FPGA IP core.
    2. In Data Direction, select Bidir.
    3. In Data width, enter 1.
    4. Turn on Use differential buffer.
    5. In Register mode, select none.
  2. Connect the modules and the input and output ports as shown in the following figure:
    Figure 6. Input and Output Ports Connection Example for Intel® Stratix® 10 Devices
  3. In the Assignment Editor, assign the relevant I/O standard as shown in the following figure. You can also set the current strength and slew rate options. Otherwise, the Intel® Quartus® Prime software assumes the default settings.
    Figure 7. BLVDS I/O Assignment in the Intel® Quartus® Prime Assignment Editor for Intel® Stratix® 10 Devices
  4. Compile and perform functional simulation with the ModelSim* - Intel® FPGA Edition software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message