AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

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ID 683803
Date 7/31/2018
Public
Document Table of Contents
Document Table of Contents
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview BLVDS Technology in Intel Devices BLVDS Power Consumption BLVDS Design Example Performance Analysis Document Revision History for AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families
BLVDS Overview
Design Considerations Effective Impedance Propagation Delay
BLVDS Technology in Intel Devices
I/O Standards for BLVDS Interface in Intel FPGA Devices
BLVDS Design Example
Design Example Guidelines for Intel® Stratix® 10 Devices Design Example Guidelines for Intel® Arria® 10 Devices Design Example Guidelines for Intel® MAX® 10 Devices Design Example Guidelines for All Supported Devices Except Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® MAX® 10
Performance Analysis
System Setup Bus Termination Stub Length Stub Termination Driver Slew Rate Overall System Performance
Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

BLVDS Overview

Typical multipoint BLVDS system consists of a number of transmitter and receiver pairs (transceivers) that are connected to the bus.
Figure 1. Multipoint BLVDS


The configuration in the preceding figure provides bidirectional half-duplex communication while minimizing interconnect density. Any transceiver can assume the role of a transmitter, with the remaining transceivers acting as receivers (only one transmitter can be active at a time). Bus traffic control, either through a protocol or hardware solution is typically required to avoid driver contention on the bus. The performance of a multipoint BLVDS is greatly affected by the capacitive loading and termination on the bus.


Section Content
Design Considerations
Effective Impedance
Propagation Delay

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