AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018

Design Considerations

A good multipoint design must consider the capacitive load and termination on the bus to obtain better signal integrity. You can minimize the load capacitance by selecting a transceiver with low pin capacitance, connector with low capacitance, and keeping the stub length short.

One of the multipoint BLVDS design consideration is the effective differential impedance of a fully loaded bus, referred to as effective impedance, and the propagation delay through the bus.

Other multipoint BLVDS design considerations include fail-safe biasing, connector type and pin-out, PCB bus trace layout, and driver edge rate specifications.