AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018
Public

BLVDS Design Example

The design example shows you how to instantiate the BLVDS I/O buffer in the supported devices with the relevant general purpose I/O (GPIO) IP cores in the Intel® Quartus® Prime software.
  • Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices—use the GPIO Intel® FPGA IP core.
  • Intel® MAX® 10 devices—use the GPIO Lite Intel® FPGA IP core.
  • All other supported devices—use the ALTIOBUF IP core.

You can download the design example from the link in the related information.

For the BLVDS I/O buffer instance, Intel recommends the following items:

  • Implement the GPIO IP core in bidirectional mode with the differential mode turned on.
  • Assign the I/O standard to the bidirectional pins:
    • BLVDS— Intel® Cyclone® 10 LP, Cyclone® IV, Cyclone® III, and Intel® MAX® 10 devices.
    • Differential SSTL-2 Class I or Class II— Stratix® V, Stratix® IV, Stratix® III, Arria® V, Arria® II, and Cyclone® V devices.
    • Differential SSTL-18 Class I or Class II— Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 GX devices.
Table 3.  Input or Output Buffers Operation During Write and Read Operations
Write Operation (BLVDS I/O Buffer) Read Operation (Differential Input Buffer)
  • Receive a serial data stream from the FPGA core through the doutp input port
  • Create an inverted version of the data
  • Transmit the data through the two single-ended output buffers connected to the p and n bidirectional pins
  • Receive the data from the bus through the p and n bidirectional pins
  • Sends the serial data to the FPGA core through the din port
  • The oe port receives the oe signal from the device core to enable or disable the single-ended output buffers.
  • Keep the oe signal low to tri-state the output buffers during read operation.
  • The function of the AND gate is to stop the transmitted signal from going back into the device core. The differential input buffer is always enabled.

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