AN 522: Implementing Bus LVDS Interface in Supported Intel® FPGA Device Families

ID 683803
Date 7/31/2018
Public

Performance Analysis

The multipoint BLVDS performance analysis demonstrates the impact of the bus termination, loading, driver and receiver characteristics, and the location of the receiver from the driver on the system.

You can use the included BLVDS design examples to analyze the performance of a multipoint application:

  • Cyclone® III BLVDS design example—this design example is applicable to all supported Stratix® , Arria® , and Cyclone® device series. For Intel® Arria® 10 or Intel® Cyclone® 10 GX device family, you need to migrate the design example to the respective device family first before you can use it.
  • Intel® MAX® 10 BLVDS design example—this design example is applicable to Intel® MAX® 10 device family.
  • Intel® Stratix® 10 BLVDS design example—this design example is applicable to Intel® Stratix® 10 device family.
Note: The performance analysis of a multipoint BLVDS in this section is based on the Cyclone® III BLVDS input/output buffer information specification (IBIS) model simulation in HyperLynx*.

Intel recommends that you use these Intel® IBIS models for simulation:

  • Stratix® III, Stratix® IV, and Stratix® V devices—device-specific Differential SSTL-2 IBIS model
  • Intel® Stratix® 10, Intel® Arria® 10 2 and Intel® Cyclone® 10 GX devices:
    • Output buffer—Differential SSTL-18 IBIS model
    • Input buffer—LVDS IBIS model
2 The Intel® Arria® 10 IBIS models are preliminary and are not available on the Intel® IBIS model web page. If you require these preliminary Intel® Arria® 10 IBIS models, contact Intel.

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