EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Status Register

Table 14.  Status Register Bits
Bit Name Value Description
7 None
6 BP3 (Block Protect Bit) 12 Table 15 through Table 20 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
5 TB (Top/Bottom Bit)
  • 1=Protected area starts from the bottom of the memory array.
  • 0=Protected area starts from the top of the memory array.
Determine that the protected area starts from the top or bottom of the memory array.
4 BP212 Table 15 through Table 20 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
3 BP112
2 BP012
1 WEL (Write Enable Latch Bit)
  • 1=Allows the following operation to run:
    • Write Bytes
    • Write Status Register
    • Erase Bulk
    • Erase Die
    • Erase Sector
  • 0=Rejects the above mentioned operations.
 Allows or rejects certain operation to run.
0 WIP (Write in Progress Bit)
  • 1=One of the following operation is in progress:
    • Write Status Register
    • Write NVCR
    • Write Bytes
    • Erase
  • 0=no write or erase cycle in progress
 Indicates if there is a command in progress.

Section Content
Read Status Register Operation (05h)
Write Status Register Operation (01h)

12 The erase bulk and erase die operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation.
Level Two Title