Supported Devices
Features
Operating Conditions
Pin Information
Device Package and Ordering Code
Memory Array Organization
Memory Operations
Registers
Summary of Operation Codes
Power Mode
Timing Information
Programming and Configuration File Support
Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0
Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)
Write Enable Operation (06h)
Write Disable Operation (04h)
Read Bytes Operation (03h)
Fast Read Operation (Bh)
Extended Quad Input Fast Read Operation (EBh)
Read Device Identification Operation (9Eh or 9Fh)
Write Bytes Operation (02h)
Extended Quad Input Fast Write Bytes Operation (12h)
Erase Bulk Operation (C7h)
Erase Die Operation (C4h)
Erase Sector Operation (D8h)
Power Mode
EPCQ-L devices support active and standby power modes. When the nCS signal is low, the device is enabled and is in active power mode. The FPGA is configured while the EPCQ-L device is in active power mode. When the nCS signal is high, the device is disabled but remains in active power mode until all internal cycles are completed, such as write or erase operations. The EPCQ-L device then goes into standby power mode. The ICC1 and ICC0 parameters list the VCC supply current when the device is in active and standby power modes. Refer to Table 5.