EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Document Revision History for EPCQ-L Serial Configuration Devices Datasheet

Document Version Changes
2018.05.18
  • Updated content of Bit 3 of the Flag Status Register from VPP to Reserved.
  • Updated the overshoot and undershoot note description in Absolute Maximum Ratings table.
2018.03.09 Added data retention feature information.
Date Version Changes
December 2017 2017.12.14
  • Added support for Intel® Cyclone® 10 GX devices.
  • Changed instances of the following:
    • Arria 10 devices to Intel® Arria® 10 devices
    • Stratix 10 devices to Intel® Stratix® 10 devices
    • Quartus Prime software to Intel® Quartus® Prime software
  • Added operation codes for the following operations:
    • Read Status Register Operation Timing Diagram
    • Write Status Register Operation Timing Diagram
    • Read Flag Status Register Operation Timing Diagram
    • Read Non-Volatile Configuration Register Operation Timing Diagram
    • Write Non-Volatile Configuration Register Operation Timing Diagram
    • 4BYTEADDREN Timing Diagram
    • 4BYTEADDREX Timing Diagram
    • Write Enable Operation Timing Diagram
    • Write Disable Operation Timing Diagram
    • Read Bytes Operation Timing Diagram
    • Fast Read Operation Timing Diagram
    • Extended Quad Input Fast Read Operation Timing Diagram
    • Read Device Identification Operation Timing Diagram
    • Write Bytes Operation Timing Diagram
    • Extended Quad Input Fast Write Bytes Operation Sequence
    • Erase Bulk Operation Timing Diagram
    • Erase Sector Operation Timing Diagram
  • Updated the operation code from binary to hex for each operation in the Operation Codes for EPCQ-L Devices table.
  • Updated the Read Flag Status Register Operation Timing Diagram.
  • Updated the note to the fast read and extended quad input fast read operations in the Operation Codes for EPCQ-L Devices table.
May 2017 2017.05.22
  • Added Read flag status register, Dual I/O fast read, and Extended dual input fast write bytes operations.
  • Updated instances of write status operation to write status register operation.
  • Added Flag Status Register Bit Content table.
  • Updated Read Status Register Operations.
  • Updated Read Status Register.
December 2016 2016.12.16
  • Updated address bytes for erase bulk and erase die to 4.
  • Added erase subsector in Operation Codes for EPCQ-L Devices table.
  • Updated tESS Max to 0.8.
October 2016 2016.10.31
  • Added Stratix 10 support.
  • Changed instances of Quartus II to Quartus Prime.
  • Changed instances of USB-Blaster to FPGA USB Download Cable.
  • Changed instances of EthernetBlaster to FPGA Ethernet Download Cable.
May 2016 2016.05.30 Updated Signals for EPCQ-L Devices table by replacing NC with DNU.
March 2016 2016.03.31 Removed 'Preliminary' terms in Address Range for EPCQ-L256, EPCQ-L512 and EPCQ-L1024.
December 2015 2015.12.14 Added link to EPCQ-L packaging information website.
January 2015 2015.01.23
  • Updated the package name to FBGA24.
  • Changed erase bulk operation statement for EPCQ-L256 devices.
  • Added stacked die device in 'Features'.
  • Added Number of die column in 'Supported Devices'.
  • Updated Read Bytes and Fast Read operation description to reflect stacked die properties.
  • Added read non-volatile configuration register.
  • Updated AS x1 dummy clock cycles for non-volatile configuration registers.
  • Updated write non-volatile configuration register 16-bit register value.
June 2014 2014.06.17 Initial release.

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