EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents

Read Operation Timing

Figure 20. Read Operation Timing Diagram
Table 27.  Read Operation Timing Parameters
Symbol Parameter Min Max Unit
fRCLK Read clock frequency (from the FPGA or embedded processor) for read bytes operations 50 MHz
Fast read clock frequency (from the FPGA or embedded processor) for fast read bytes operation 100 MHz
tCH DCLK high time 4 ns
tCL DCLK low time 4 ns
tODIS Output disable time after read 8 ns
tnCLK2D Clock falling edge to DATA 7 ns

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