EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Non-Volatile Configuration Register

Table 22.  Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration Register Operation
FPGA Device Address Bytes Dummy Clock Cycles
AS x1 AS x4
Intel® Arria® 10 and Intel® Cyclone® 10 GX 4-byte addressing 10 10
Intel® Stratix® 10 4-byte addressing — 10
Table 23.  Non-Volatile Configuration Register Operation Bit Definition
Bit Description Default Value
15:12 Number of dummy cycles. When this number is from 0001 to 1110, the dummy cycles is from 1 to 14. 0000 or 1111 15 16
11:5 Set these bits to 1111111. 1111111
4 Don't care. 1
3:1 Set these bits to 111. 111
0 Address byte setting. 17
  • 0—4-byte addressing
  • 1—3-byte addressing
1

Section Content
Read Non-Volatile Configuration Register Operation (B5h)
Write Non-Volatile Configuration Register Operation (B1h)

15 The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended dual input fast and standard fast read.
16 For the Intel® Stratix® 10 device, use the default value 1111h to set 10 dummy clock cycles.
17 You can only configure the Intel® Arria® 10 and Intel® Cyclone® 10 GX devices using the 4-byte addressing mode.
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