EPCQ-L Serial Configuration Devices Datasheet

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ID 683710
Date 5/18/2018
Public
Document Table of Contents
Document Table of Contents x
EPCQ-L Serial Configuration Devices Datasheet
EPCQ-L Serial Configuration Devices Datasheet x
Supported Devices Features Operating Conditions Pin Information Device Package and Ordering Code Memory Array Organization Memory Operations Registers Summary of Operation Codes Power Mode Timing Information Programming and Configuration File Support Document Revision History for EPCQ-L Serial Configuration Devices Datasheet
Operating Conditions x
Absolute Maximum Ratings Recommended Operating Conditions DC Operating Conditions ICC Supply Current Capacitance
Pin Information x
EPCQ-L Device Pin Description
Device Package and Ordering Code x
Package Ordering Code
Memory Array Organization x
Address Range for EPCQ-L256 Address Range for EPCQ-L512 Address Range for EPCQ-L1024
Memory Operations x
Timing Requirements Addressing Mode
Registers x
Status Register Flag Status Register Non-Volatile Configuration Register
Status Register x
Read Status Register Operation (05h) Write Status Register Operation (01h)
Read Status Register Operation (05h) x
Block Protection Bits in EPCQ-L256 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L256 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L512 when TB Bit is Set to 1 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 0 Block Protection Bits in EPCQ-L1024 when TB Bit is Set to 1
Flag Status Register x
Read Flag Status Register Operation(70h)
Non-Volatile Configuration Register x
Read Non-Volatile Configuration Register Operation (B5h) Write Non-Volatile Configuration Register Operation (B1h)
Summary of Operation Codes x
4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h) Write Enable Operation (06h) Write Disable Operation (04h) Read Bytes Operation (03h) Fast Read Operation (Bh) Extended Quad Input Fast Read Operation (EBh) Read Device Identification Operation (9Eh or 9Fh) Write Bytes Operation (02h) Extended Quad Input Fast Write Bytes Operation (12h) Erase Bulk Operation (C7h) Erase Die Operation (C4h) Erase Sector Operation (D8h)
Timing Information x
Write Operation Timing Read Operation Timing
EPCQ-L Serial Configuration Devices Datasheet

Write Status Register Operation (01h)

The write status register operation does not affect the write enable latch and write in progress bits. You can use the write status register operation to set the status register block protection and top or bottom bits. Therefore, you can implement this operation to protect certain memory sectors. Refer to Table 15 through Table 20. After setting the block protect bits, the protected memory sectors are treated as read-only memory. You must execute the write enable operation before the write status operation.

When the operation is in progress, the write or erase controller bit of the flag status register is set to 0. To obtain the operation status, the flag status register must be polled13, with nCS toggled twice in between commands. When the operation completes, the write or erase controller bit is cleared to 1. The end of operation can be detected when the flag status register outputs the write or erase controller bit to 1 each time it is polled.

The following figure shows the timing diagram for the write status register operation.

Figure 3. Write Status Register Operation Timing Diagram

Immediately after the nCS signal drives high, the device initiates the self-timed write status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ-L devices and is guaranteed to be less than 8 ms. For details about tWS , refer to Table 26. You must account for this delay to ensure that the status register is written with the desired block protect bits. Alternatively, you can check the write in progress bit in the status register by executing the read status register operation while the self-timed write status cycle is in progress. The flash controller sets the write in progress bit to 1 during the self-timed write status cycle and 0 when it is complete.

13 Poll the flag status register once for EPCQL256, twice for EPCQL512 or four times for EPQL1024.
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