EPCQ-L Serial Configuration Devices Datasheet

ID 683710
Date 5/18/2018
Document Table of Contents

Write Status Register Operation (01h)

The write status register operation does not affect the write enable latch and write in progress bits. You can use the write status register operation to set the status register block protection and top or bottom bits. Therefore, you can implement this operation to protect certain memory sectors. Refer to Table 15 through Table 20. After setting the block protect bits, the protected memory sectors are treated as read-only memory. You must execute the write enable operation before the write status operation.

When the operation is in progress, the write or erase controller bit of the flag status register is set to 0. To obtain the operation status, the flag status register must be polled13, with nCS toggled twice in between commands. When the operation completes, the write or erase controller bit is cleared to 1. The end of operation can be detected when the flag status register outputs the write or erase controller bit to 1 each time it is polled.

The following figure shows the timing diagram for the write status register operation.

Figure 3. Write Status Register Operation Timing Diagram

Immediately after the nCS signal drives high, the device initiates the self-timed write status cycle. The self-timed write status cycle usually takes 5 ms for all EPCQ-L devices and is guaranteed to be less than 8 ms. For details about tWS , refer to Table 26. You must account for this delay to ensure that the status register is written with the desired block protect bits. Alternatively, you can check the write in progress bit in the status register by executing the read status register operation while the self-timed write status cycle is in progress. The flash controller sets the write in progress bit to 1 during the self-timed write status cycle and 0 when it is complete.

13 Poll the flag status register once for EPCQL256, twice for EPCQL512 or four times for EPQL1024.

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